About me
I am a Master's degree student at the University of Florida who loves working on projects related to Computer Architecture, Embedded Systems, Internet of Things and EDA development.
I completed my Bachelors of Technology at SRM Institute of Science and Technology in July, 2020 and started my Masters in Fall 2021.
My previous stint with Keydabra as an Engineer taught me a lot about testing paradigms and it sparked an interest in EDA automation and code generation techniques for Computer Architecture design.
Currently I am interested in designing in-order pipelined processors, high-performance algorithm accelerators, vector extension cores, RISC-V based pipelined structures, and have worked on other cool software projects such as a RISC-V Assembler, Chip-8 Emulator and Automatic Verilog Testbench Generator.
My future plans are to work on vector-based reconfigurable processors and extending that to architect RISC-V based structures. As of now, my research has been more human-centric embedded solutions, but since May 2020, I have been researching on theoretical computer architecture. Checkout my projects and papers to get an idea about my interests!
My previous stint with Keydabra as an Engineer taught me a lot about testing paradigms and it sparked an interest in EDA automation and code generation techniques for Computer Architecture design.
Currently I am interested in designing in-order pipelined processors, high-performance algorithm accelerators, vector extension cores, RISC-V based pipelined structures, and have worked on other cool software projects such as a RISC-V Assembler, Chip-8 Emulator and Automatic Verilog Testbench Generator.
My future plans are to work on vector-based reconfigurable processors and extending that to architect RISC-V based structures. As of now, my research has been more human-centric embedded solutions, but since May 2020, I have been researching on theoretical computer architecture. Checkout my projects and papers to get an idea about my interests!